LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY fs_mux2to1 IS
  PORT( 
  i0  : IN     STD_LOGIC;
  i1  : IN     STD_LOGIC;
  s   : IN     STD_LOGIC;
  y    : OUT    STD_LOGIC
  );
END ENTITY fs_mux2to1;

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-----------------------------------
ARCHITECTURE v OF fs_mux2to1 IS
BEGIN
  
  
  y <= i0 WHEN s = '0' ELSE
       i1;
  
  
  
END ARCHITECTURE v;

